Senior Verification Manager

I am currently recruiting for a Senior Verification Manager - to work for a major semiconductor company, based near the beautiful south coast of France.

You will be managing an R&D team - made up of engineers who have a mix of hardware and software skills - for complex verification tasks on the latest developments for the semiconductor industry.

The ideal candidate will have a mix of functional and formal verification experience, as well as good control of a variety of software languages - like C++, java, python etc.

• ASIC & FPGA, at IP & SOC level.
• Expert knowledge of UVM and System verilog.
• Formal verification - SVA / system verilog assertions, jasper gold, VC Formal, Siemens EDA, OneSpin, MathWorks
• Software verification - python, CocoTB
• HW-SW interface
• Modelling - System C, TLM, UML
• Software development methodologies / frameworks - AGILE, Jira, Scrum, Kanban, OOP, DevOps - CI / CD, automation etc.
• Additional knowledge of IC design and architecture is a bonus
• Fluent English, plus French is preferred / a bonus.
• EU working rights. Visa sponsorship will be considered on a case by case basis

Previous team management experience is a MUST.

Salary will be based on seniority and relevance of experience, circa €100-150k + excellent benefits & package.