Emplacement

Biot
France
France

Contrat

À plein temps, Durée indéterminée

Date de publication:

2026-11-10

Online to:

2027-01-09
EUR 15.00 HOUR

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Principal Design Verification Engineer

ARTERIS IP
France
40 minutes il y a

h3Description /h3p strong Do you want to contribute to the backbone of some of the world’s most popular SoCs? /strong /pp As a strong Senior Staff / Principal Design Verification Engineer /strong at Arteris, you will work with an expert team to design and deliver interconnect memory hierarchy solutions for some of the world#39;s most sophisticated mobile, telecom, automotive, and consumer SoC designs. You will create designs in a powerful language that blends traditional RTL with leading-edge software to provide extremely configurable, testable, and high-quality solutions. You will go home at the end of the day, amazed at all the places where your creations end up. You will have the opportunity to be part of a proven, successful startup, and to influence the development environment, architecture, verification, and everything in-between – you will no longer be stuck in a silo or just a cog in the machine. Your co-workers will be an experienced team of industry experts who love what they do. /pp strong Key Responsibilities: /strong /pul no-style="background-repeat: no-repeat;outline: none;margin: 1.0em 0.0px;padding: 0.0px 0.0px 0.0px 40.0px;list-style: inside disc;font-family: #39;Open Sans#39; , Helvetica;font-size: 14.0px;font-style: normal;font-weight: 400;letter-spacing: normal;text-indent: 0.0px;text-transform: none;word-spacing: 0.0px;"li UVM based test bench development and debugging /lili Defining, documenting, developing, and executing RTL verification test/coverage at the system level /lili Triaging Regressions, Debugging RTL designs in Verilog and System Verilog /lili Help improve and refine the verification process, methodology, and metrics /lili Develop, maintain, and test engineering design automation tools infrastructure to improve our frontend design and verification process. /lili Monitor automated systems, isolate problems, and perform routine diagnostics checks repairs. /lili Run regressions, configure Jenkins builds, and record regression data /lili Build/maintain regression dashboards database to view trends and progress in numerical and graphical formats /lili Evaluate existing automation infrastructure for areas of improvement /lili Provide clear, concise documentation of the implementation/flow and usage of automation processes. /li /ulp strong Experience Requirements / Qualifications: /strong /pul no-style="background-repeat: no-repeat;outline: none;margin: 1.0em 0.0px;padding: 0.0px 0.0px 0.0px 40.0px;list-style: inside disc;font-family: #39;Open Sans#39; , Helvetica;font-size: 14.0px;font-style: normal;font-weight: 400;letter-spacing: normal;text-indent: 0.0px;text-transform: none;word-spacing: 0.0px;"li Verification flow enhancements using a scripting language such as Shell scripts, Python JavaScript /lili Strong RTL (Verilog) and UVM/C test bench debugging skills /lili Experience integrating vendor-provided VIPs for unit and system-level verification /lili Experience with Arm AMBA protocols /lili This opportunity involves high-performance, low-power designs on a highly visible project /li /ulp strong Education Requirements: /strong /pul no-style="background-repeat: no-repeat;outline: none;margin: 1.0em 0.0px;padding: 0.0px 0.0px 0.0px 40.0px;list-style: inside disc;font-family: #39;Open Sans#39; , Helvetica;font-size: 14.0px;font-style: normal;font-weight: 400;letter-spacing: normal;text-indent: 0.0px;text-transform: none;word-spacing: 0.0px;"li MS degree in EE, CS, or equivalent preferred. BS degree minimum. /li /ul

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Principal Design Verification Engineer

Emplacement

Contrat

Date de publication:

Online to:

Principal Design Verification Engineer

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