Digital Verification Engineer – SoC / Subsystem / Mixe…

Digital Verification Engineer – SoC / Subsystem / Mixed-Signal (Semiconductor / ASIC)

We are currently partnered with an innovative semiconductor company developing advanced mixed-signal and digital processing ASICs. They are looking to hire a Digital Verification Engineer to join their growing verification team, working across subsystem and SoC-level verification of complex, state-of-the-art designs.

Key responsibilities

• Write subsystem and top-level verification plans aligned with ASIC functional requirements
• Develop and maintain verification methodologies, contributing to continuous improvements in verification flows
• Build subsystem and SoC-level testbenches and self-checking test cases
• Implement RTL and GLS (Gate-Level Simulation) regressions, including coverage-driven verification metrics
• Support analog design teams through mixed-signal simulation activities

Key requirements

• MSc or PhD in Electrical Engineering or equivalent discipline
• Hands-on experience in digital verification
• Strong understanding of digital electronics and signal processing fundamentals
• Solid experience with SystemVerilog and/or UVM testbench development
• Strong scripting skills (Python, Tcl, Makefiles or similar automation tools)

Keywords:

Digital Verification / SoC / Subsystem / SystemVerilog / UVM / GLS / RTL / Coverage / AMBA / AXI / APB / AHB / CPU Verification / RISC-V / ARM / PCIe / Ethernet / Mixed-Signal / ASIC / Emulation / Silicon Validation / Python / Tcl / Semiconductor

If you are interested in this position, please send your cv to Alistair@eu-recruit.com

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