Digital Verification Engineer - ASIC / Semiconductors

Digital Verification Engineer - ASIC / Semiconductors

We are partnered with a fabless semiconductor leader specializing in high-speed data converters and complex Mixed-Signal SoCs. The team is looking for a Digital Verification Engineer to drive the verification of state-of-the-art ASICs from subsystem to top-level.

This is a permanent opportunity that can be based remotely within France or from offices in Paris, Caen, or Grenoble.

Key responsibilities for this Digital Verification Engineer position:

• Author subsystem and top-level plans to meet stringent ASIC functional requirements.
• Build self-checking testbenches and test cases using SystemVerilog/UVM.
• Execute RTL and Gate Level Simulations (GLS), managing coverage metrics to ensure closure.
• Collaborate with Analog design teams to facilitate complex mixed-signal simulations.
• Support software teams on emulation platforms and assist Silicon Validation teams with lab evaluation.
• Participate in verification flow enhancements and QA-standard test procedures.

Key requirements:

• 3+ years of hands-on experience in Digital Verification.
• Solid proficiency in SystemVerilog
• Experience with UVM methodology.
• Strong background in digital electronics and signal processing.
• Expert scripting skills in Python, Tcl, or Makefiles.
• Experience Plus: Knowledge of AMBA buses (AXI/AHB), CPU verification (RISC-V/ARM), or high-speed interfaces (PCIe, Ethernet).

Keywords: Digital Verification Engineer / SystemVerilog / UVM / ASIC / SoC / RTL / Gate Level Simulation / Python / Mixed-Signal / RISC-V / AMBA / Paris / Grenoble / Caen / Remote

If you are interested in this Digital Verification Engineer position, please send a CV to ts@eu-recruit.com

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